Location(s): Santa Clara, California

The Team

The PortalPlayer ASIC team defines, designs and verifies high performance integrated circuits used in internet audio and digital media solutions. Check us out at www.portalplayer.com.

The Job

The Senior ASIC Design Engineer is responsible for using best-in-class design methodologies to design functional modules for Digital Media System-on-a-Chip products. Specific design responsibilities depend on the candidate's background and may include vector floating point units, cache controllers, DMA engines, networking interfaces, memory controllers and/or media streams processors. Tasks may include:

• Define design specifications in collaboration with other team members
• RTL coding using Verilog
• Functional verification using logic simulation and/or FPGAs with ARM test code
• Synthesis and scan insertion
• Static timing analysis
• Code coverage
• Silicon validation

Qualification

Candidates must meet the following minimum requirements:

• BSEE or equivalent(MSEE preferred)
• Three or more years of experience in synthesizeable Verilog or VHDL coding
• Proven track record of clean ASIC designs
• Able to work effectively in a team environment
• Desire to work hard, play hard and get pre-IPO stock options!

And someone with this background will definitely get our attention:

• Experience with NC Verilog and Synopsys synthesis and STA tools
• Familiarity with digital media processing and consumer audio standards
• Familiarity with ARM embedded processors and AMBA standard buses
• Knowledge of timing-driven physical design methodologies for deep sub-micron design

If you fit the above profile, then e-mail your resume to us.hwjobs@portalplayer.com today!

Job Posting #HW032
Approved 1/2/01
Reports to Director of ASIC Design

Back to Employment Listings >>